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| 1 ? fn6520.3 isl6333, isl6333a, isl6333b, isl6333c three-phase buck pwm controller with integrated mosfet drivers and light load efficiency enhancements for intel vr11.1 applications the isl6333 three-phase pwm family of control ics provide a precision voltage regulation system for advanced microprocessors. the integratio n of power mosfet drivers into the controller ic marks a departure from the separate pwm controller and driver configur ation of previous multi-phase product families. by reducing the number of external parts, this integration is optimized for a cost and space saving power management solution. the isl6333 controllers are designed to be compatible with intel vr11.1 applications. featur es that make these controllers compatible include an imon pin for output current monitoring, and a power state indicator (psi#) pin for phase dropping and higher efficiency during light l oad states. an 8-bit vid input is used to select the desired out put voltage from the vr11 dac table. a circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. the output voltage can also be positively or negatively offset through the use of a single external resistor. the isl6333 controllers also include advanced control loop features for optimal transient response to load application and removal. one of these features is highly accurate, fully differential, continuous dcr current sensing for load line programming and channel current balance. active pulse positioning (app) modulation and adaptive phase alignment (apa) are two other unique features, allowing for quicker initial response to high di/dt load transients. with this quicker initial response to load transients, the number of output bulk capacitors can be reduced, helping to reduce cost. integrated into the isl6333 cont rollers are user-programmable current sense resistors, which require only a single external resistor to set their values. no external current sense resistors are required. another unique feat ure of the isl6333 controllers is the addition of a dynamic vid compensation pin that allows optimizing compensation to be added for well-controlled dynamic vid response. protection features of these controller ics include a set of sophisticated overvoltage, un dervoltage, and overcurrent protection. furthermore, t he isl6333 controllers include protection against an open circuit on the remote sensing inputs. combined, these features provid e advanced protection for the microprocessor and power system. features ? intel vr11.1 compatible - imon pin for output current monitoring - power state indicator (psi#) pin for phase dropping and higher efficiency during light load states ? cpurst_n input to elimi nate required extensive external circuit for proper psi# operation of intel?s eaglelake chipset platform (isl6333b, isl6333c only) ? integrated multi-ph ase power conversion - 3-phase or 2-phase operation with internal drivers ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over-temperature - adjustable reference-voltage offset ? optimal transient response - active pulse positioning (app) modulation - adaptive phase alignment (apa) ? fully differential, continuous dcr current sensing - integrated programmable current sense resistors - accurate load line programming - precision channel current balancing ? gate voltage optimization technology (isl6333, isl6333b only) ? power saving diode emulation mode (isl6333, isl6333b only) ? optimized for use with coupled inductors ? variable gate drive bias: +5v to +12v ? microprocessor voltag e identification inputs - 8-bit vid input for selecting vr11 dac voltages - dynamic vid technology ? dynamic vid compensation ? overcurrent protection and channel current limit ? multi-tiered overvoltage protection ? digital soft-start ? selectable operation frequency up to 1.0mhz per phase ? pb-free (rohs compliant) data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 8, 2010
2 fn6520.3 october 8, 2010 ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6333crz* isl6333 crz 0 to +70 48 ld 7x7 qfn l48.7x7 isl6333irz* isl6333 irz -40 to +85 48 ld 7x7 qfn l48.7x7 isl6333acrz* isl6333a crz 0 to +70 48 ld 7x7 qfn l48.7x7 ISL6333AIRZ* isl6333a irz -40 to +85 48 ld 7x7 qfn l48.7x7 isl6333bcrz* isl6333b crz 0 to +70 48 ld 7x7 qfn l48.7x7 isl6333birz* isl6333b irz -40 to +85 48 ld 7x7 qfn l48.7x7 isl6333ccrz* isl6333c crz 0 to +70 48 ld 7x7 qfn l48.7x7 isl6333cirz* isl6333c irz -40 to +85 48 ld 7x7 qfn l48.7x7 *add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. pinouts isl6333 (48 ld qfn) top view isen1+ isen1- isen2+ isen2- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 isen3+ isen3- pvcc1 byp1 lgate1 boot1 ugate1 phase1 rgnd vsen imon psi# vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_rdy en puvcc phase2 ugate2 boot2 lgate2 pvcc2_3 lgate3 boot3 ugate3 phase3 rset ofs fs ss vcc ref apa comp dvc fb idroop vdiff gnd (pin 49) isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 3 fn6520.3 october 8, 2010 isl6333a (48 ld qfn) top view isl6333b (48 ld qfn) top view pinouts (continued) isen1+ isen1- isen2+ isen2- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 isen3+ isen3- pvcc1 pvcc2 lgate1 boot1 ugate1 phase1 rgnd vsen imon psi# vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_rdy en puvcc phase2 ugate2 boot2 lgate2 pvcc3 lgate3 boot3 ugate3 phase3 rset ofs fs ss vcc ref apa comp dvc fb idroop vdiff gnd (pin 49) isen1+ isen1- isen2+ isen2- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 isen3+ isen3- pvcc1 byp1 lgate1 boot1 ugate1 phase1 rgnd vsen imon psi# vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_rdy en puvcc phase2 ugate2 boot2 lgate2 pvcc2_3 lgate3 boot3 ugate3 phase3 rset ofs fs ss vcc ref apa comp dvc fb cpurst_n vdiff gnd (pin 49) isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 4 fn6520.3 october 8, 2010 isl6333c (48 ld qfn) top view controller descriptions and comments controller diode emulation mode (dem) gate voltage optimization technology (gvot) droop pin enable/disable droop cpurst_n pin isl6333 yes yes yes enable/disable no isl6333a no no yes enable/disable no isl6333b yes yes no always enabled yes isl6333c no no no always enabled yes controller comments isl6333 when psi# is set high, the controller operates normally in continuous conduction mode (ccm) with all active channels fir ing. when the psi# pin is set low, the contro ller transitions to single phase operation and changes to diode emulation mode (dem). the controller also utilizes it?s new gate voltage optimizati on technology (gvot) to reduce channel 1?s lower mosfet gate drive voltage. this controller yiel ds the highest low load efficiency. isl6333a when psi# is set high, the controller operates normally in continuous conduction mode (ccm ) with all active channels fi ring. when the psi# pin is set low, the controlle r transitions to single phase operation only. isl6333b same feature set as the isl6333 controller with two addi tional changes. the cpurst_n pin is added to eliminate extensiv e external circuitry required for proper psi# operation of in tel?s eaglelake chipset platform. the droop pin has been removed and the droop current now flows out of the fb pin. the droop feat ure is always active. this c ontroller yields the highest low load efficiency. isl6333c same feature set as the isl6333a controller with two additional changes. the cpurst_n pin is added to eliminate extensi ve external circuitry required for proper psi# operation of in tel?s eaglelake chipset platform. the droop pin has been removed and the droop current now flows out of the fb pin. the droop feature is always active. pinouts (continued) isen1+ isen1- isen2+ isen2- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 isen3+ isen3- pvcc1 pvcc2 lgate1 boot1 ugate1 phase1 rgnd vsen imon psi# vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_rdy en puvcc phase2 ugate2 boot2 lgate2 pvcc3 lgate3 boot3 ugate3 phase3 rset ofs fs ss vcc ref apa comp dvc fb cpurst_n vdiff gnd (pin 49) isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 5 fn6520.3 october 8, 2010 integrated driver block diagram through shoot- protection boot ugate phase lgate logic control gate uvcc 10k pwm soft-start 20k low power state and fault logic lvcc isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 6 fn6520.3 october 8, 2010 block diagram - isl6333 driver dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp 1 n pwm1 boot2 ugate2 phase2 lgate2 pvcc2_3 soft-start and fault logic vcc reset power-on 0.85v en vr_rdy gnd vid1 vid0 channel overvoltage detection logic undervoltage detection logic pwm2 i_avg mosfet adaptive phase allignment circuitry ocp i_trip i_avg imon apa isen2- isen2+ isen1+ isen1- rset x2 dvc clock and channel detect fs r isen2 r isen1 1k + + pwm3 ch3 isen3- isen3+ r isen3 + driver boot3 ugate3 phase3 lgate3 mosfet driver boot1 ugate1 phase1 lgate1 mosfet pvcc1 ldo byp1 idroop rgnd vsen vdiff x1 open sense line prevention current balance and current limit app and apa modulator modulator waveform generator app and apa modulator app and apa modulator low power psi# state circuitry ss i_avg current sense ch2 current sense ch1 current sense ss puvcc ocp v ocp ocp rgnd isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 7 fn6520.3 october 8, 2010 block diagram - isl6333a driver dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp 1 n pwm1 boot2 ugate2 phase2 lgate2 pvcc3 soft-start and fault logic vcc reset power-on 0.85v en vr_rdy gnd vid1 vid0 channel overvoltage detection logic undervoltage detection logic pwm2 i_avg mosfet adaptive phase allignment circuitry ocp i_trip i_avg imon apa isen2- isen2+ isen1+ isen1- rset x2 dvc clock and channel detect fs r isen2 r isen1 1k + + pwm3 ch3 isen3- isen3+ r isen3 + driver boot3 ugate3 phase3 lgate3 mosfet driver boot1 ugate1 phase1 lgate1 mosfet pvcc1 pvcc2 idroop rgnd vsen vdiff x1 open sense line prevention current balance and current limit app and apa modulator modulator waveform generator app and apa modulator app and apa modulator low power psi# state circuitry ss i_avg current sense ch2 current sense ch1 current sense puvcc ocp v ocp ocp rgnd isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 8 fn6520.3 october 8, 2010 block diagram - isl6333b driver dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp 1 n pwm1 boot2 ugate2 phase2 lgate2 pvcc2_3 soft-start and fault logic vcc reset power-on 0.85v en vr_rdy gnd vid1 vid0 channel overvoltage detection logic undervoltage detection logic pwm2 i_avg mosfet adaptive phase allignment circuitry ocp i_trip i_avg imon apa isen2- isen2+ isen1+ isen1- rset x2 dvc clock and channel detect fs r isen2 r isen1 1k + + pwm3 ch3 isen3- isen3+ r isen3 + driver boot3 ugate3 phase3 lgate3 mosfet driver boot1 ugate1 phase1 lgate1 mosfet pvcc1 ldo byp1 rgnd vsen vdiff x1 open sense line prevention current balance and current limit app and apa modulator modulator waveform generator app and apa modulator app and apa modulator low power psi# state circuitry ss i_avg current sense ch2 current sense ch1 current sense ss puvcc ocp v ocp ocp rgnd cpurst_n isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 9 fn6520.3 october 8, 2010 block diagram - isl6333c driver dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp 1 n pwm1 boot2 ugate2 phase2 lgate2 pvcc3 soft-start and fault logic vcc reset power-on 0.85v en vr_rdy gnd vid1 vid0 channel overvoltage detection logic undervoltage detection logic pwm2 i_avg mosfet adaptive phase allignment circuitry ocp i_trip i_avg imon apa isen2- isen2+ isen1+ isen1- rset x2 dvc clock and channel detect fs r isen2 r isen1 1k + + pwm3 ch3 isen3- isen3+ r isen3 + driver boot3 ugate3 phase3 lgate3 mosfet driver boot1 ugate1 phase1 lgate1 mosfet pvcc1 pvcc2 rgnd vsen vdiff x1 open sense line prevention current balance and current limit app and apa modulator modulator waveform generator app and apa modulator app and apa modulator low power psi# state circuitry ss i_avg current sense ch2 current sense ch1 current sense puvcc ocp v ocp ocp rgnd cpurst_n isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 10 fn6520.3 october 8, 2010 typical application diag ram - isl6333, isl6333b vid4 vid5 vr_rdy vid3 vid2 vid1 vcc isl6333/b vid0 fs ofs ref load en gnd vid6 vid7 ss +5v isen3- isen3+ isen1- isen1+ imon fb comp vsen rgnd dvc phase1 ugate1 boot1 lgate1 +12v phase3 ugate3 boot3 lgate3 rset apa +5v vcc isen2- isen2+ phase2 ugate2 boot2 lgate2 +12v pvcc2_3 +12v puvcc byp1 psi# vdiff idroop pvcc1 1.8 1.8 1.8 rgnd cpurst_n *note: isl6333 - connect the idroop pin to the fb pin. the cpurst_n pin does not exist. *note: isl6333b - the cpurst_n pin should connect to the cpurst_n signal. the idroop pin does not exist. isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 11 fn6520.3 october 8, 2010 typical application diagram - isl6333, is l6333b with ntc thermal compensation vid4 vid5 vr_rdy vid3 vid2 vid1 vcc isl6333/b vid0 fs ofs ref load en gnd vid6 vid7 +5v isen3- isen3+ isen1- isen1+ fb comp vsen rgnd dvc phase1 ugate1 boot1 lgate1 +12v phase3 ugate3 boot3 lgate3 rset apa +5v vcc isen2- isen2+ phase2 ugate2 boot2 lgate2 +12v pvcc2_3 puvcc psi# vdiff idroop ntc place in close proximity +12v byp1 pvcc1 1.8 1.8 1.8 ss imon rgnd cpurst_n *note: isl6333 - connect the idroop pin to the fb pin. the cpurst_n pin does not exist. *note: isl6333b - the cpurst_n pin should connect to the cpurst_n signal. the i droop pin does not exist. isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 12 fn6520.3 october 8, 2010 typical application di agram - isl6333a, isl6333c vid4 vid5 vr_rdy vid3 vid2 vid1 vcc isl6333a vid0 fs ofs ref load en gnd vid6 vid7 +5v isen3- isen3+ isen1- isen1+ fb comp vsen rgnd dvc phase1 ugate1 boot1 lgate1 +12v phase3 ugate3 boot3 lgate3 rset apa +5v vcc isen2- isen2+ phase2 ugate2 boot2 lgate2 +12v pvcc3 +12v puvcc pvcc2 psi# vdiff idroop pvcc1 1.8 1.8 1.8 ss imon rgnd cpurst_n *note: isl6333a - connect the idroop pin to the fb pin. the cpurst_n pin does not exist. *note: isl6333c - the cpurst_n pin s hould connect to the cpurst_n signa l. the idroop pin does not exist. isl6333, isl6333a, isl6333b, isl6333c isl6333, isl6333a, isl6333b, isl6333c 13 fn6520.3 october 8, 2010 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage, v boot . . . . . . . gnd - 0.3v to gnd + 36v phase voltage, v phase . . . . . . . . . gnd - 8v (<400ns, 20j) to 30v (<200ns, v boot - v gnd < 36v) ugate voltage, v ugate . . . . . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate voltage, v lgate . . . . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc + 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v thermal information thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 28 1.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature isl6333crz, isl6333acrz, isl6333bcrz, isl6333ccrz . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c isl6333irz, ISL6333AIRZ, isl6333birz, isl6333cirz . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions. boldface limits apply over the operating temperature range. parameter test conditions min (note 4) typ max (note 4) units bias supplies input bias supply current i vcc ; en = high 13 16.7 19.5 ma lower gate drive bias current - pvcc1 pin i pvcc1 ; en = high 0.7 1.8 4 ma lower gate drive bias current - pvcc2_3 pin (isl6333, isl6333b only) i pvcc2_3 ; en = high 1.5 2.6 5 ma lower gate drive bias current - pvcc3 pin (isl6333a, isl6333c only) i pvcc3 ; en = high 1.5 2.6 5 ma upper gate drive bias current - puvcc pin i uvcc ; en = high 0.6 1 1.4 ma vcc por (power-on reset) threshold vcc rising 4.25 4.41 4.50 v vcc falling 3.75 3.85 4.00 v pvcc por (power-on reset) threshold pvcc1, pvcc2_3, puvcc rising 4.30 4.42 4.55 v pvcc1, pvcc2_3, puvcc falling 3.70 3.83 3.95 v byp1 por (power-on reset) threshold byp1 rising 4.20 4.40 4.55 v byp1 falling 3.70 3.80 3.90 v pwm modulator oscillator frequency accuracy, f sw (isl6333crz, isl6333acrz, isl6333bcrz, isl6333ccrz) r t = 100k ( 0.1%) 225 250 275 khz oscillator frequency accuracy, f sw (isl6333irz, ISL6333AIRZ, isl6333birz, isl6333cirz) r t = 100k ( 0.1%) (note 3) 215 250 280 khz adjustment range of switching frequency (note 3) 0.08 - 1.0 mhz isl6333, isl6333a, isl6333b, isl6333c 14 fn6520.3 october 8, 2010 oscillator ramp amplitude, v p-p (note 3) - 1.50 - v control thresholds en rising threshold 0.84 0.86 0.88 v en hysteresis 96 104 120 mv reference and dac system accuracy (1.000v to 1.600v) -0.5 - 0.5 % system accuracy (0.600v to 1.000v) -1.0 - 1.0 % system accuracy (0.400v to 0.600v) -2.0 - 2.0 % dac input low voltage - - 0.4 v dac input high voltage 0.8 - - v psi# input psi# input low voltage threshold - - 0.4 v psi# input high voltage threshold 0.8 - - v pin-adjustable offset ofs sink current accuracy (negative offset) r ofs = 32.4k from ofs to vcc -52.0 -50.3 -48.0 a ofs source current accuracy (positive offset) r ofs = 6.04k from ofs to gnd 47.0 48.7 51.0 a error amplifier dc gain r l = 10k to ground, (note 3) - 96 - db gain-bandwidth product c l = 100pf, r l = 10k to ground, (note 3) - 40 - mhz slew rate c l = 100pf, load = 400a, (note 3) - 20 - v/s maximum output voltage load = 1ma 4.00 4.196 - v minimum output voltage load = -1ma - 1.231 1.60 v soft-start ramp soft-start ramp rate r s = 100k 1.15 1.274 1.37 mv/s adjustment range of soft-start ramp rate (note 3) 0.156 - 6.25 mv/s current sensing idroop current sense offset r set = 40.2k , v isen1+ = v isen2+ = 0v -2.5 0 2.5 a idroop current sense gain r set = 40.2k , v isen1 = v isen2 = 24mv 77.5 81.2 85 a overcurrent protection overcurrent trip level - average channel normal operation 88 100 110 a dynamic vid change 120 140 160 a overcurrent trip level - individual channel normal operation 120 138 160 a dynamic vid change 170 195 222 a imon pin clamped overcurrent level 1.1 1.127 1.15 v overvoltage and undervoltage protection undervoltage threshold vsen falling 0.48*vdac 0.503*vdac 0.525*vdac v undervoltage hysteresis vsen rising 0.02*vdac 0.084*vdac 0.15*vdac v electrical specifications recommended operating conditions. boldface limits apply over the operating temperature range. (continued) parameter test conditions min (note 4) typ max (note 4) units isl6333, isl6333a, isl6333b, isl6333c 15 fn6520.3 october 8, 2010 timing diagram overvoltage threshold during soft-start 1.260 1.280 1.300 v overvoltage threshold vr11, vsen rising vdac + 160mv vdac + 175mv vdac + 194mv v overvoltage hysteresis vsen falling 90 108 120 mv switching time (note 3) ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current - 2.0 - upper drive sink resistance v pvcc = 12v, 15ma sink current - 1.35 - lower drive source resistance v pvcc = 12v, 15ma source current - 1.35 - lower drive sink resistance v pvcc = 12v, 15ma sink current - 0.90 - over-temperature shutdown (note 3) thermal shutdown setpoint - 160 - c thermal recovery setpoint - 100 - c notes: 3. limits established by characte rization and are not production tested. 4. parameters with min and/or max limits are 100% tested at + 25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions. boldface limits apply over the operating temperature range. (continued) parameter test conditions min (note 4) typ max (note 4) units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate isl6333, isl6333a, isl6333b, isl6333c 16 fn6520.3 october 8, 2010 functional pin descriptions vcc vcc is the bias supply for the ics small-signal circuitry. connect this pin to a +5v supply and decouple using a quality 0.1f ceramic capacitor. pvcc1 (isl6333, isl6333b only) this pin is the input to an internal ldo that regulates the voltage on the byp1 pin and should be connected to a +12v supply. it is very important that this pin is decoupled using a quality 1.0f ceramic capacitor. pvcc2_3 (isl6333, isl6333b only) this pin is the power supply pin for channels 2 and 3 lower mosfet drivers, and should be connected to a +12v supply. decouple this pin with a quality 1.0f ceramic capacitor. pvcc1, pvcc2, and pvcc3 (isl6333a, isl6333c only) these pins are the power supply pins for channels 1, 2, and 3 lower mosfet drivers, and should be connected to a +12v supply. decouple these pins with quality 1.0f ceramic capacitors puvcc this pin is the power supply pin for channels 1, 2, and 3 upper mosfet drivers, and can be connected to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1.0f ceramic capacitor. byp1 (isl6333, isl6333b only) this pin is the output of an internal ldo which powers channel 1 lower mosfet driver. a quality 1.0f ceramic capacitor should be placed from this pin to ground. gnd gnd is the bias and reference ground for the ic. en this pin is a threshold-sensitive (approximately 0.86v) enable input for the controllers. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fs a resistor, r fs , tied from this pin to ground sets the channel switching frequency of the controller. refer to equation 46 for proper resistor calculation. the fs pin also determines whether the controllers operate in the coupled inductor mode or the standard inductor mode of operation. tying the r fs resistor to ground will set the controllers to operate in standard inductor mode. tying the r fs resistor to vcc sets the controllers to operate in coupled inductor mode. vid0, vid1, vi d2, vid3, vid4, vid5, vid6, and vid7 these are the inputs for the in ternal dac that provide the reference voltage for output regulation. these pins respond to ttl logic thresholds. these pins are internally pulled high to approximately 1.2v, by 40a internal current sources. the internal pull-up current decreases to 0 as the vid voltage approaches the internal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ic?s bias voltage (vcc). vsen and rgnd vsen and rgnd are inputs to the precision differential remote-sense amplifier and should be connected to the sense pins of the remote load. vdiff vdiff is the output of the differential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd. fb and comp these pins are the internal error amplifier inverting input and output respectively. the fb pin, comp pin, and the vdiff pins are tied together thr ough external r-c networks to compensate the regulator. dvc a series resistor and capacitor can be connected from the dvc pin to the fb pin to compensate and smooth dynamic vid transitions. idroop (isl6333, isl6333a only) the idroop pin is the average channel-current sense output. connecting this pin directly to fb allows the converter to incorporate output voltage droop proportional to the output current. if voltage droop is not desired leave this pin unconnected. imon the imon pin is the average channel-current sense output. this pin is used as a load current indicator to monitor the output load current. apa this is the adaptive phase alignment set pin. a 100a current flows into the apa pin and by tying a resistor from this pin to comp the trip level for the adaptive phase alignment circuitry can be set. ref the ref input pin is the positive inpu t of the error amplifier. it is internally connected to the dac output through a 1k resistor. a capacitor is used between the ref pin and ground to smooth the voltage transition during soft-start and dynamic vid transitions. this pin can also be bypassed to rgnd if desired. isl6333, isl6333a, isl6333b, isl6333c 17 fn6520.3 october 8, 2010 rset connect this pin to vcc through a resistor to set the effective value of the internal r isen current sense resistors. it is recommended a 0.1f ceramic capacitor be placed in parallel with this resistor for noise immunization. ofs the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vsen. the offset current is generated via an external resistor and precision internal vo ltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. isen1-, isen1+, isen2-, isen2+, isen3-, and isen3+ these pins are used for differentially sensing the corresponding channel output currents. the sensed currents are used for channel balancing, protection and load line regulation. connect isen1-, isen2-, and isen3- to the node between the rc sense elements surrounding the inductor of their respective channel. tie the isen+ pins to the vcore side of their corresponding channel?s sense capacitor. tying isen3- to vcc programs the part for two-phase operation. ugate1, ugate2, and ugate3 connect these pins to their corresponding upper mosfet gates through 1.8 resistors. these pins are used to control the upper mosfets and are monitored for shoot-through prevention purposes. boot1, boot2, and boot3 these pins provide the bias voltage for the corresponding upper mosfet drives. connect these pins to appropriately chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pin provides the necessary bootstrap charge. phase1, phase2, and phase3 connect these pins to the sources of the corresponding upper mosfets. these pins ar e the return path for the upper mosfet drives. lgate1, lgate2, and lgate3 these pins are used to control the lower mosfets. connect these pins to the corresponding lower mosfets? gates. ss a resistor, r ss , placed from ss to ground or vcc, will set the soft-start ramp slope. refer to equations 20 and 21 for proper resistor calculation. on the isl6333 and isl6333b the ss pin also determines what voltage level the intern al ldo regulates the byp1 pin to when psi# is low. tying the r ss resistor to ground regulates byp1 to 5.75v. tying the r ss resistor to vcc, regulates byp1 to 7.75v. vr_rdy vr_rdy indicates whether vdiff is within specified overvoltage and undervoltage limit s after a fixed delay from the end of soft-start. it is an open-drain logic output. if vdiff exceeds these limits, an overcurrent event occurs, or if the part is disabled, vr_rdy is pulled low. vr_rdy is always low prior to the end of soft-start. psi# the psi# pin is a digital logic input pin used to indicate whether the controllers should be in a low power state of operation or not. when psi# is high the controllers will run in it?s normal power state. when ps i# is low the controllers will change their operating state to improve light load efficiency. the controllers resume normal operation when this pin is pulled high again. cpurst_n (isl6333b, isl6333c only) the cpurst_n pin is a digital logic input pin used in conjunction with the psi# pin to indicate whether the isl6333b and isl6333c should be in a lower power state of operation or not. if cpurst_n is high, the operating state of the controllers can be changed to improve light load efficiency by setting psi# low. if cpur st_n is low, the controllers cannot be put into it?s light load operating state. once cpurst_n toggles high again, there is a 50ms delay before the controllers are allowed to enter a low power state. operation multi-phase power conversion microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. designing a regulator t hat is cost-effective, thermally sound, and efficient has become a challenge that only multi- phase converters can accomp lish. the isl6333 family of controllers help simplify implem entation by integrating vital functions and requiring minima l external components. the block diagrams provide a top level view of multi-phase power conversion using the isl6333 family of controllers. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out- of-phase with each of the other channels. in a 3-phase converte r, each channel switches 1/3 cycle after the previous chan nel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency 3x greater than the ripple frequency of any one phase. in addition , the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. isl6333, isl6333a, isl6333b, isl6333c 18 fn6520.3 october 8, 2010 . figure 1 illustrates the multiplica tive effect on output ripple frequency. the three channel currents (i l1 , i l2 , and i l3 ) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. active pulse po sitioning (app) modulated pwm operation the controllers use a proprietary active pulse positioning (app) modulation scheme to control the internal pwm signals that command each channel?s driver to turn their upper and lower mosfets on and off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is th e inverse of the switching frequency set by the resistor connected to the fs pin. the advantage of intersil?s proprietary active pulse positioning (app) modulator is that the pwm signal has the ability to turn on at any point during this pwm time interval, and turn off immediately after the pwm signal transitions high. this is important because it allows the controllers to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp minus the current correction signal relative to the proprietary modulator ramp waveform as illustrated in figure 4. at the beginning of each pwm time interval, this modified v comp signal is compared to the internal modulator waveform. as long as the modified v comp voltage is lower then the modulator waveform voltage, the pwm signal is commanded low. the internal mosfet driver detects the low state of the pwm signal and turns off the figure 1. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm2, 5v/div pwm1, 5v/div i l2 , 7a/div i l1 , 7a/div i l1 + i l2 + i l3 , 7a/div i l3 , 7a/div pwm3, 5v/div (eq. 1) i pp v in v out ? () v out ? lf s v ? in ? --------------------------------------------------------- - = (eq. 2) i cpp () v in nv out ? ? () v out ? lf s v ? in ? ------------------------------------------------------------------- - = figure 2. channel input currents and input-capacitor rms current for 3-phase converter channel 1 input current channel 2 input current channel 3 input current input-capacitor current, 10a/div 1s/div isl6333, isl6333a, isl6333b, isl6333c 19 fn6520.3 october 8, 2010 upper mosfet and turns on the lower synchronous mosfet. when the modified v comp voltage crosses the modulator ramp, the pwm output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm signal will remain high until the modified v comp voltage crosses the modulator ramp again. when this occurs the pwm signal will transition low again. during each pwm time interval, the pwm signal can only transition high once. once pwm transitions high it cannot transition high again until the beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. adaptive phase alignment (apa) to further improve the transi ent response, the controllers also implement intersil?s proprietary adaptive phase alignment (apa) technique, which turns on all of the channels together at the same time during large current step, high di/dt transient events. as figure 3 shows, the apa circuitry works by monitoring the voltage on the apa pin and comparing it to a filtered copy of the voltage on the comp pin. the voltage on the apa pin is a copy of the comp pin voltage that has been negatively offset. if the apa pin exceeds the filtered comp pin voltage an apa event occurs and all of the channels are forced on. the apa trip level is the am ount of dc offset between the comp pin and the apa pin. this is the voltage excursion that the apa and comp pin must have during a transient event to activate the adaptive phase alignment circuitry. this apa trip level is set through a resistor, r apa , that connects from the apa pin to the comp pin. a 100a current flows across r apa into the apa pin to set the apa trip level as described in equation 3. an apa trip level of 500mv is recommended for most applications. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. number of active channels the default number of active channels on the controllers is three for 3-phase operation. if 2-phase operation is desired, the isen3- pin should be tied to the vcc pin. this will disable channel 3, so only channel 1 and 2 will fire. in 2-phase operation all of the channel 3 pins should be left unconnected including t he phase3, lgate3, ugate3, boot3, and isen3+ pins. psi# (low power state) operation the controllers are designed to operate in both their normal power state for high efficiency at heavy loads, and a low power state to increase the regulator?s light load efficiency. the power state of the regula tor is controlled by the psi# pin, which is a digital logic input. when this pin is set high the regulators will operate in their normal power state, with all active channels firing in continuous conduction mode (ccm). when the psi# pin is set low the controllers change their operating state to the low power state to increase light load efficiency. the different controllers have different low power operating states as described in table 1 and the following sections. it?s important to note that during soft-start and dynamic vid transitions the psi# pin is ignored and the controllers are forced to run in their normal power state. the state of the psi# pin is considered again at the end of a successful soft-start sequence or dynamic vid transition. isl6333, isl6333b low power state on the isl6333 and isl6333b, when the psi# pin is set low, the controllers change their operating state in multiple ways. first, all active channels are turned off accept for channel 1. channel 1 continues to operate but does so in diode emulation mode (dem). dem only allows the upper and lower mosfets to turn on to al low positive current to flow through the output inductor. if the inductor current falls to 0a during a switching cycle, both the lower and upper mosfets are turned off to allow no negative current to build up in the inductor. this helps to decrease the conduction losses of the mosfets and the inductor at very low load currents. when the isl6333 and isl6333b are operating in dem, it?s important for the controllers to know whether the output inductors are standard inductors or coupled inductors. pwm operation is optimized for use with coupled inductors by minimizing switching losses and body-diode conduction figure 3. adaptive phase alignment detection external circuit isl6333 internal circuit comp v apa,trip error apa amplifier c apa r apa + - low filter - + apa pass 100a - + to apa circuitry v apa trip () r apa 100 10 6 ? ? = (eq. 3) table 1. power state operation description controller psi# phase count ccm or dem gvot isl6333, isl6333b high 3/2-phase ccm yes low 1-phase dem yes isl6333a, isl6333c high 3/2-phase ccm no low 1-phase ccm no isl6333, isl6333a, isl6333b, isl6333c 20 fn6520.3 october 8, 2010 losses. the fs pin determine s whether the controllers operate in the coupled inductor mode or the standard inductor mode of operation. tying the fs pin resistor, r fs , to ground will set the controllers to operate in standard inductor mode. tying the r fs resistor to vcc sets the controllers to operate in coupled inductor mode. when psi# is set low, the isl6333 and isl6333b also utilize the new gate voltage optimization technology (gvot) to reduce channel 1 lower mosfet gate drive voltage. the controllers are designed to optimize the channel 1 lower mosfet gate drive voltage to ensure high efficiency in both normal and low power states. in the low power state where the conver ter load current is low, mosfet driving loss is a higher percentage of the power loss associated with the lower mosfet. in low power state, the lower gate drive voltage can therefore be reduced to decrease the driving losses of the lower mosfets and increase the system efficiency. more informatio n about this can be found in the ?gate voltage optimization technology (gvot) (isl6333, isl6333b only)? on page 27. when the psi# pin is set high, the controllers will immediately begin returning the regulator to it?s normal power state, by turning on all the active channels, placing them in ccm mode, and increasing the channel 1 lower gate drive voltage back to it?s original level. isl6333a, isl6333c low power state on the isl6333a and isl6333c, when the psi# pin is set low, the controllers change thei r operating state by turning off all active channels accept for channel 1. this is the only change made to the regulator. channel 1 continues to operate in ccm just as it does in the normal power state. when the psi# pin is set high , the controllers immediately begin returning the regulator to it?s normal power state, by turning on all the active channels. cpurst_n operation (isl6333b, isl6333c only) the isl6333b and isl6333c both include a cpurst_n pin which can be utilized by microprocessors that have a cpurst_n output. the cpurst_n pin is a digital input used in conjunction with the psi# pin to indicate whether the controllers should be in a lower power state of operation or not. if cpurst_n is high, the operating state of the controllers is controlled by the psi# pin. if cpurst_n is low, the controllers will only run in their normal power state and cannot be put into their light load power state. once cpurst_n toggles high again, there is a 50ms delay before the controllers recognize the state of the psi# pin. channel current balance one important benefit of multi-phase operation is the thermal advantage gained by distributi ng the dissipated heat over multiple devices and greater area. by doing this the designer avoids the complexity of driving parallel mosfets and the expense of using expensive hea t sinks and exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry equal amounts of current at any load level. to achieve this, the currents through each channel must be sensed continuously every switching cy cle. the sensed currents, i sen , from each active chann el are summed together and divided by the number of active channels. the resulting cycle average current, i avg , provides a measure of the total load-current demand on the converter during each switching cycle. channel current balance is achieved by comparing the sensed current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patented current-balance method is illustrated in figure 4, with error correction for channel 1 repres ented. in the figure, the cycle average current, i avg , is compared with the channel 1 sensed current, i sen1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. figure 4. channel-1 pwm function and current-balance adjustment n i avg i sen3 i sen2 - + + - + - f(s) pwm1 i sen1 v comp i er note: channel 3 is optional. filter to gate control logic modulator ramp waveform figure 5. continuous current sampling time pwm i l i sen switching period isl6333, isl6333a, isl6333b, isl6333c 21 fn6520.3 october 8, 2010 continuous current sensing in order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. during this time the current-sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the controllers support inductor dcr current sensing to continuously sense each channel?s current for channel-current balance. the internal circuitry, shown in figure 6 represents one channel of the controller. th is circuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating. inductor windings have a characteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 6. the channel current i l , flowing through the inductor, passes through the dcr. equation 4 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor (r 1 and c) extracts the dcr voltage, as shown in figure 6. the voltage across the sense capacitor, v c , can be shown to be proportional to the channel current i l , shown in equation 5. if the r 1 -c 1 network components are selected such that their time constant matches the induct or l/dcr time constant, then v c is equal to the voltage drop across the dcr. the capacitor voltage v c , is then replicated across the effective internal sense resistance, r isen . this develops a current through r isen which is proportional to the inductor current. this current, i sen , is continuously sensed and is then used by the controllers for load-line regulation, channel-current balancing, and overcurrent detection and limiting. equation 6 shows t hat the proportion between the channel-current, i l , and the sensed current, i sen , is driven by the value of the effective sense resistance, r isen , and the dcr of the inductor. the effective internal r isen resistance is important to the current sensing process because it sets the gain of the load line regulation loop as well as the gain of the channel-current balance loop and the overcurrent trip level. the effective internal r isen resistance is user programmable and is set through use of the r set pin. placing a single resistor, r set , from the r set pin to the vcc pin programs the effective internal r isen resistance according to equation 7. the current sense circuitry operates in a very similar manner for negative current feedback, where inductor current is flowing from the output of the regulator to the phase node, opposite of flow pictured in figure 6. however, the range of proper operation with negative current sensing is limited to ~60% of full positive current ocp threshold. care should be taken to avoid operation with negative current feedback exceeding this threshold, as this may lead to momentary loss of current balance betwe en phases and disruption of normal circuit operation. output voltage setting the controllers use a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the vid pins. the dac decodes the logic signals into one of the discrete voltages shown in table 2. each vid pin is pulled up to an internal 1.2v voltage by a weak current source (40a), which decreases to 0a as the voltage at the vid pin varies from 0 to the internal 1.2v pull-up voltage. external pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5v. figure 6. inductor dcr current sensing configuration i n - + isen- sense isl6333 internal v in ugate r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen v c (s) + - isen+ lgate mosfet driver rset r set vcc circuit v l s () i l sl dcr + ? () ? = (eq. 4) v c s () sl ? dcr ------------- 1 + ?? ?? sr 1 c 1 ?? 1 + () ----------------------------------------- dcr i l ? ? = (eq. 5) table 2. vr11 voltage identification codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 00000000off 00000001off 000000101.6 0000 000000111.5 9375 000001001.5 8750 000001011.5 8125 000001101.5 7500 i sen i l dcr r isen ----------------- - ? = (eq. 6) r isen 3 400 --------- - r set ? = (eq. 7) isl6333, isl6333a, isl6333b, isl6333c 22 fn6520.3 october 8, 2010 000001111.56875 000010001.56250 000010011.55625 000010101.55000 000010111.54375 000011001.53750 000011011.53125 000011101.52500 000011111.51875 000100001.51250 000100011.50625 000100101.50000 000100111.49375 000101001.48750 000101011.48125 000101101.47500 000101111.46875 000110001.46250 000110011.45625 000110101.45000 000110111.44375 000111001.43750 000111011.43125 000111101.42500 000111111.41875 001000001.41250 001000011.40625 001000101.40000 001000111.39375 001001001.38750 001001011.38125 001001101.37500 001001111.36875 001010001.36250 001010011.35625 001010101.35000 001010111.34375 001011001.33750 001011011.33125 001011101.32500 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 001011111.3 1875 001100001.3 1250 001100011.3 0625 001100101.3 0000 001100111.2 9375 001101001.2 8750 001101011.2 8125 001101101.2 7500 001101111.2 6875 001110001.2 6250 001110011.2 5625 001110101.2 5000 001110111.2 4375 001111001.2 3750 001111011.2 3125 001111101.2 2500 001111111.2 1875 010000001.2 1250 010000011.2 0625 010000101.2 0000 010000111.1 9375 010001001.1 8750 010001011.1 8125 010001101.1 7500 010001111.1 6875 010010001.1 6250 010010011.1 5625 010010101.1 5000 010010111.1 4375 010011001.1 3750 010011011.1 3125 010011101.1 2500 010011111.1 1875 010100001.1 1250 010100011.1 0625 010100101.1 0000 010100111.0 9375 010101001.0 8750 010101011.0 8125 010101101.0 7500 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6333, isl6333a, isl6333b, isl6333c 23 fn6520.3 october 8, 2010 010101111.06875 010110001.06250 010110011.05625 010110101.05000 010110111.04375 010111001.03750 010111011.03125 010111101.02500 010111111.01875 011000001.01250 011000011.00625 011000101.00000 011000110.99375 011001000.98750 011001010.98125 011001100.97500 011001110.96875 011010000.96250 011010010.95625 011010100.95000 011010110.94375 011011000.93750 011011010.93125 011011100.92500 011011110.91875 011100000.91250 011100010.90625 011100100.90000 011100110.89375 011101000.88750 011101010.88125 011101100.87500 011101110.86875 011110000.86250 011110010.85625 011110100.85000 011110110.84375 011111000.83750 011111010.83125 011111100.82500 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 011111110.8 1875 100000000.8 1250 100000010.8 0625 100000100.8 0000 100000110.7 9375 100001000.7 8750 100001010.7 8125 100001100.7 7500 100001110.7 6875 100010000.7 6250 100010010.7 5625 100010100.7 5000 100010110.7 4375 100011000.7 3750 100011010.7 3125 100011100.7 2500 100011110.7 1875 100100000.7 1250 100100010.7 0625 100100100.7 0000 100100110.6 9375 100101000.6 8750 100101010.6 8125 100101100.6 7500 100101110.6 6875 100110000.6 6250 100110010.6 5625 100110100.6 5000 100110110.6 4375 100111000.6 3750 100111010.6 3125 100111100.6 2500 100111110.6 1875 101000000.6 1250 101000010.6 0625 101000100.6 0000 101000110.5 9375 101001000.5 8750 101001010.5 8125 101001100.5 7500 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6333, isl6333a, isl6333b, isl6333c 24 fn6520.3 october 8, 2010 voltage regulation the integrating compensation net work shown in figure 7, insures that the steady-state error in the output voltage is limited only to the error in t he reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the controllers to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is compared to the modulator waveform to generate the pwm signals. the pwm signals control the timing of the internal mosfet drivers and regulate the converte r output so that the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 8. the internal and external circuitry that controls voltage regulation is illustrated in figure 7. the controllers incorporate an internal differential remote-sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non-inverting input, vsen, and in verting input, rgnd, of the remote-sense amplifier. the remote sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. load line (droop) regulation some microprocessor manufact urers require a precisely controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load line regulation required by these manufacturers. in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output voltage spike that results from fast load current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors select ed. by positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 7, a current proportional to the average current of all active channels, i avg , flows from the idroop pin through a load line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output vo ltage droop with a steady-state value defined as equation 9: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a function of load current is derived by combining equations 6, 7, 8, and 9. 101001110.56875 101010000.56250 101010010.55625 101010100.55000 101010110.54375 101011000.53750 101011010.53125 101011100.52500 101011110.51875 101100000.51250 101100010.50625 101100100.50000 11111110off 11111111off table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac v out v ref v ofs ? v droop ? = (eq. 8) figure 7. output voltage and load-line regulation with offset adjustment i avg external circuit isl6333 internal circuit comp r c r fb fb vdiff vsen rgnd - + (v droop + v ofs ) error - + v out + differential remote-sense amplifier v comp c c ref c ref - + v out - idroop vid dac 1k amplifier i ofs (eq. 9) v droop i avg r fb ? = (eq. 10) v out v ref v ofs ? i out n ------------- dcr r set --------------- 400 3 --------- - r fb ??? ?? ?? ?? ? = isl6333, isl6333a, isl6333b, isl6333c 25 fn6520.3 october 8, 2010 in equation 10, v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the internal sens e resistor connected to the isen+ pin, r fb is the feedback resistor, n is the active number of channels, and dcr is the inductor dcr value. therefore the equivalent loadl ine impedance, i.e. droop impedance, is equal to equation 11: output-voltage offset programming the controllers allow the desig ner to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin, providing a negative offset. if r ofs is connected to ground, the voltage across it is regulated to 0.3v, and i ofs flows into the fb pin and out of the ofs pin, providing a positive offset. the offset current flowing through the resistor between vsen and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 8 and 9. once the desired output offset voltage has been determined, use equations 12 and 13 to set r ofs : for negative offset (connect r ofs to vcc): for positive offset (connect r ofs to gnd): dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operatio n. they direct the controllers to do this by making changes to the vid inputs. the controllers are required to monitor the dac inputs and respond to on-the-fly vid changes in a controlled manner, supervising a safe output vo ltage transition without discontinuity or disruption. the controllers check for vid changes by comparing the internal dac code to the vid pin inputs on the positive edge of an internal 5.55mhz clock. if a new code is established on the vid inputs and it remains stable for 3 consecutive readings (360ns to 540ns), the controllers recognize the new code and begins incrementing/decrementing the dac in 6.25mv steps at a stepping frequency of 1.85mhz. this controlled slew rate of 6.25m v/540ns (11.6mv/s) continues until the vid input and dac are equal. thus, the total time required for a vid change, t dvid , is dependent only on the size of the vid change ( v vid ). the time required for a isl6333-based converter to make a 1.6v to 0.5v reference voltage change is about 95s, as calculated using equation 14. vid ?off? dac codes the intel vr11 vid tables include ?off? dac codes, which indicate to the controllers to disable all regulation. recognition of these codes is slightly different in that they must be stable for 4 consecutive readings of a 5.55mhz clock (540ns to 720ns) to be recognized. once an ?off? code is recognized the controllers latch off, and must be reset by toggling the en pin. r ll r fb n ------------ dcr r set --------------- 400 3 --------- - ?? = (eq. 11) e/a fb ofs vcc gnd + - + - 0.3v 1.6v gnd r ofs r fb vdiff figure 8. positive offset output voltage programming vref v ofs + - i ofs isl6333 internal circuit (eq. 12) r ofs 1.6 r fb ? v offset -------------------------- = (eq. 13) r ofs 0.3 r fb ? v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.3v 1.6v vcc r ofs r fb vdiff figure 9. negative offset output voltage programming vref v ofs + - i ofs isl6333 internal circuit (eq. 14) t dvid 540 10 9 ? v vid 0.00625 --------------------- ?? ?? ?? = isl6333, isl6333a, isl6333b, isl6333c 26 fn6520.3 october 8, 2010 compensating dynamic vid transitions during a vid transition, the resulting change in voltage on the fb pin and the comp pin causes an ac current to flow through the error amplifier compensation components from the fb to the comp pin. this current then flows through the feedback resistor, r fb , and can cause the output voltage to overshoot or undershoot at the end of the vid transition. in order to ensure the smooth transition of the output voltage during a vid change, a vid-on-the-fly comp ensation network is required. this network is composed of a resistor and capacitor in series, r dvc and c dvc , between the dvc and the fb pin. this vid-on-the-fly compensation network works by sourcing ac current into the fb node to offset the effects of the ac current flowing from the fb to the comp pin during a vid transition. to create th is compensation current the controllers set the voltage on the dvc pin to be 2x the voltage on the ref pin. since the error amplifier forces the voltage on the fb pin and the ref pin to be equal, the resulting voltage across the series rc between dvc and fb is equal to the ref pin voltage. the rc compensation components, r dvc and c dvc , can then be selected to create the desired amount of compensation current. the amount of compensation cu rrent required is dependant on the modulator gain of the system, k1, and the error amplifier r- c components, r c and c c , that are in series between the fb and comp pins. use equations 15, 16, and 17 to calculate the rc component values, r dvc and c dvc , for the vid-on-the-fly compensation network. for these equations: v in is the input voltage for the power train; v p-p is the oscillator ramp amplitude (1.5v); and r c and c c are the error amplifier r-c components between the fb and comp pins. driver operation adaptive zero shoot-through deadtime control the integrated drivers incorporat e an adaptive deadtime control technique to minimize deadtime and to prevent the upper and lower mosfets from conducting simultaneously. this results in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lower mosfet, the lgate voltage is monitored until it reac hes 1.75v. at this time the ugate is released to rise. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase falls to less than +0.8v, the lgate is released to turn on. internal bootstrap device all three integrated drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor should have a maximum voltage rating that?s at least 30% above pvcc and its capacitance value can be chosen from equation 18: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. figure 10. dynamic vid compensation network isl6333 internal circuit error ref amplifier c dvc r dvc - + x2 c c r c c ref dvc fb comp r fb vdiff i dvc i c i dvc = i c v dac k1 v in v pp ----------- = (eq. 15) a k1 k1 1 ? ---------------- - = r dvc ar c = (eq. 16) c dvc c c a ------- - = (eq. 17) c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 18) 50nc 20nc figure 11. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap (f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc isl6333, isl6333a, isl6333b, isl6333c 27 fn6520.3 october 8, 2010 . gate voltage optimization technology (gvot) (isl6333, isl6333b only) the isl6333 and isl6333b are designed to optimize the channel 1 lower mosfet gate drive voltage to ensure high efficiency in both normal and low power states. in the normal power state when the converte r load current is high, the conduction losses of the lower mosfets play a large role in the overall system ef ficiency. in normal power state, the lower gate drive voltage should be higher to decrease the conduction losses of the lower mosfets and increase the system efficiency. in the low power state, where the converter load current is si gnificantly smaller, mosfet driving loss becomes a much higher percentage of power loss associated with the lower mosfet. in low power state, the lower gate drive voltage can therefore be reduced to decrease the driving losses of the lower mosfets and increase the system efficiency. this gate drive voltage optimization is accomplished by an internal linear regulator that regulates the channel 1 lower gate drive voltage, lvcc1, to certain levels depending on the state of the psi# and ss pi ns. the input and output of this internal regulator is the pvcc1 pin and byp1 pin, respectively. the regulator input, pvcc1, should be connected to a +12v source and decoupled with a quality 1.0f ceramic capacitor. t he regulator output, byp1, is internally connected to the lower gate drive of the channel 1 mosfet driver, lvcc1. the byp1 pin should also be decoupled using a quality 1.0f ceramic capacitor. as figures 13 and 14 illustrate, the internal regulator has been designed so that its output voltage, byp1, is dependent upon the average load current. in the normal power state, when psi# is high, the isl6333 and isl6333b regulate byp1 to around 11.2v at a 50ma average load current. in the low power state, when psi# is low, byp1 is regulated down to one of two voltages depending on the state of the ss pin. if the ss pin is tied to ground through the r ss resistor, byp1 is regulated down to 5.75v at a 50ma average load current. if the ss pin is tied to vcc through the r ss resistor, byp1 is regulated down to 7.75v at a 50ma average load current. it is possible to disable the internal gvot regulator by shorting the pvcc1 pin to the byp1 pin. this essentially bypasses the internal regulator setting the channel 1 lower gate drive voltage, lvcc1, to the voltage input on the pvcc1 pin. figure 12. internal gate drive connections and gave voltage optimization (gvot) external circuit isl6333, isl6333b internal circuit pvcc2_3 +12v pvcc1 byp1 puvcc lvcc1 1.0 f lvcc2, lvcc3 uvcc1, uvcc2, uvcc3 +5v to +12v +12v 1.0f 1.0 f 1.0f lvcc = lower gate drive uvcc = upper gate drive set by state of psi# and ss pins gvot reg. figure 13. byp1, lvcc1 voltage when psi# is high 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 0 20406080100120 average load current (ma) +40c thermal byp1, lvcc1 voltage (v) figure 14. byp1, lvcc1 voltage when psi# is low 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 byp1, lvcc1 voltage (v) average load current (ma) 0 20 40 60 80 100 120 +40c thermal r ss tied to vcc r ss tied to gnd isl6333, isl6333a, isl6333b, isl6333c 28 fn6520.3 october 8, 2010 upper mosfet gate drive voltage versatility the controllers provide the user flexibility in choosing the upper mosfet gate drive voltage for efficiency optimization. the controllers ti e all the upper gate drive rails together to the puvcc pin. simply applying a voltage from +5v up to +12v on puvcc sets all of the upper gate drive rail voltages simultaneously. initialization prior to initialization, proper conditions must exist on the en, vcc, pvcc1, pvcc2_3, puvcc, byp1 and vid pins. when the conditions are met, the c ontrollers begin soft-start. once the output voltage is within the proper window of operation, the controllers assert vr_rdy. enable and disable while in shutdown mode, the lgate and ugate signals are held low to assure the mosfets remain off. the following input conditions must be met before the controllers are released from shutdown mode to begin the soft-start startup sequence: 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the controllers are guarante ed. hysteresis between the rising and falling thresholds assure that once enabled, the controllers will not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications? on page 13). 2. the voltage on en must be above 0.86v. the enable comparator holds the controllers in shutdown until the voltage at en rises above 0.86v. the enable comparator has 104mv of hysteresis to prevent bounce. 3. the driver bias voltage applied at the pvcc1, pvcc2_3, pvcc2, pvcc3, puvcc, and byp1 pins must reach the internal power-on reset (por) rising threshold. hysteresis between the rising and falling thresholds assure that once enabled, the controllers will not inadvertently turn off unless the bias voltages drops substantially (see ?electrical specifications? on page 13). once all of these conditions are met the controllers will begin the soft-start sequence and will ramp the output voltage up as described in ?soft-start? on page 28. soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. the soft-start sequence is composed of four periods, as shown in figure 16. once the controllers are released from shutdown and soft-start begins (as described in ?enable and disable? on page 28), there will be a fixed delay period, t d1 , of typically 1.10ms. after this delay period, the controllers will begin the first soft-start ramp, increasing the output voltage until it reac hes the 1.1v vboot voltage. the controllers will then regulate the output voltage at 1.1v for another fixed delay period, t d3 , of typically 93s. at the end of the t d3 period, the controllers will read the vid signals. it is recommended that the vid codes be set no later then 50s into period t d3 . if the vid code is valid, the controllers will initiate the second soft-start ramp, regulating the output voltage up to the vid voltage any offset or droop voltage. the soft-start time is the sum of the 4 periods as shown in equation 19. during t d2 and t d4 , the controllers digitally control the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator, which is defined by the resistor r ss on the ss pin. the soft-start figure 15. power sequencing using threshold-sensitive enable (en) function isl6333 internal circuit - + 0.86v en por circuit enable comparator soft-start and fault logic vcc pvcc1 pvcc2_3 puvcc byp1 figure 16. soft-start waveforms v out , 500mv/div en 500s/div t d1 t d3 t d4 t d5 vr_rdy t d2 t ss t d1 t d2 t d3 t d4 +++ = (eq. 19) isl6333, isl6333a, isl6333b, isl6333c 29 fn6520.3 october 8, 2010 ramp times, t d2 and t d4 , can be calculated based on equations 20 and 21: for example, when vid is set to 1.5v and the r ss is set at 100k , the first soft-start ramp time t d2 will be 880s and the second soft-start ramp time t d4 will be 320s. after the dac voltage reaches the final vid setting, vr_rdy will be set to high with the fixed delay t d5 . the typical value for t d5 is 93s. pre-biased soft-start the controllers also have the ability to start up into a pre-charged output, without causing any unnecessary disturbance. the fb pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the dac setting. should the output be pre-charged to a level exceeding the dac setting, the ou tput drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the dac-set level. fault monitoring and protection the controllers actively monitor the output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common vr_rdy indicator is provided for linking to external system monitors. the schematic in figure 18 outlines the interaction between the fault monitors and the vr_rdy signal. vr_rdy signal the vr_rdy pin is an open-drain logic output that signals whether or not the controllers are regulating the output voltage within the proper levels, and whether any fault conditions exist. this pin should be tied through a resistor to a voltage source that?s equal to or less then vcc. vr_rdy indicates whether vdiff is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft-start. vr_rdy transitions low when an undervoltage, overvoltage, or ov ercurrent condition is detected or when the controllers are disabled by a reset from en, por, or one of the no-cpu vid codes. in the event of an overvoltage or overcurrent condition, or a no-cpu vid code, the controllers latch off and vr_rdy will not return high until en is toggled and a successful soft-start is completed. in the case of an undervoltage event, vr_rdy will return high when the output voltage rises above the undervoltage hysteresis level. vr_rdy is always low prior to the end of soft-start. overvoltage protection the controllers constantly moni tor the difference between the vsen and rgnd voltages to detect if an overvoltage event occurs. during soft-start, whil e the dac is ramping up, the overvoltage trip level is the high er of a fixed voltage 1.280v or dac + 175mv. upon successful soft-start, the overvoltage trip level is only dac + 175mv. when the output voltage rises above the ovp trip level actions are taken by the controllers to protect the microprocessor load. at the inception of an overvo ltage event, lgate1, lgate2, and lgate3 are commanded high and the vr_rdy signal is driven low. this turns on the all of the lower mosfets and (eq. 20) t d2 1.1 r ? ss 810 3 ? s () ?? = (eq. 21) t d4 v vid 1.1 ? r ss 810 3 ? s () ??? = figure 17. soft-start waveforms for isl6333-based multi-phase converter en (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level figure 18. power good and protection circuitry - + dac - + ovp uv vr_rdy soft-start, fault and control logic 1.280v isl6333 internal circuitry vdiff +175mv - + v ocp ocp - + ocl i 1 repeat for each channel 140a imon - + 100a i avg ocp 0.50xdac isl6333, isl6333a, isl6333b, isl6333c 30 fn6520.3 october 8, 2010 pulls the output voltage below a level that might cause damage to the load. the lgate outputs remain high until vdiff falls 110mv below the ovp threshold that tripped the overvoltage protection circuitry. the controllers will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends the controllers latch off, and must be reset by toggling en, or through por, before a soft -start can be reinitiated. there is an ovp condition that ex ists that will not latch off the controllers. during a soft-start sequence, if the vdiff voltage is above the ovp threshold an overvoltage event will occur, but will be released once vdiff falls 110mv below the ovp threshold. if vdiff then rises above the ovp trip threshold a second time, the controllers will be latched off and cannot be restarted until the controllers are reset. pre-por overvoltage protection prior to the controller and driver bias pins exceeding their por levels, the controllers ar e designed to protect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvoltage event ceases or the input power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. in the event that during normal operation the controller or driver bias voltages fall back below their por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events. undervoltage detection the undervoltage threshold is set at dac*0.50v of the vid code. when the output voltage (vdiff) is below the undervoltage threshold, vr_rdy gets pulled low. no other action is taken by the controllers. vr_rdy will return high if the output voltage rises above dac*0.60v. open sense line prevention in the case that either of the remote sense lines, vsen or gnd, become open, the controllers are designed to prevent the regulator from regulating. this is accomplished by means of a small 5a pull-up current on vsen, and a pull-down current on rgnd. if the sense lines are opened at any time, the voltage difference between v sen and r gnd will increase until an overvolt age event occurs, at which point overvoltage protection ac tivates and the controllers stop regulating. the controllers will be latched off and cannot be restarted until they are reset. overcurrent protection the controllers take advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. two different methods of detecting overcurrent events ar e available on the controllers. the first method continually compares the average sense current with a constant 100a ocp reference current, as shown in figure 18. once the average sense current exceeds the ocp reference current, a comparator triggers the converter to begin overcu rrent protection procedures. for this first method the overcu rrent trip threshold is dictated by the dcr of the inductors, the number of active channels, and the rset pin resistor, r set . to calculate the overcurrent trip level, i ocp , using this method use equation 22, where n is the number of active channels, dcr is the individual inductor?s dcr, and r set is the rset pin resistor value. during vid-on-the-fly transitions the overcurrent trip level for this method is boosted to prevent false overcurrent trip events that can occur. starting from the beginning of a dynamic vid transition, the over current trip level is boosted to 140a. the ocp level will stay at this boosted level until 50s after the end of the dynam ic vid transition, at which point it will return to the typical 100a trip level. the second method for detecting overcurrent events continuously compares the voltage on the imon pin, v imon , to the overcurrent protection voltage, v ocp , as shown in figure 18. the average channel sense current flows out the imon pin and through r imon , creating the imon pin voltage which is proportional to the output current. when the imon pin voltage exceeds the v ocp voltage threshold, the overcurrent protection circuitry activates. since the imon pin voltage is proportional to the output current, the overcurrent trip level, i ocp , can be set by selecting the proper value for r imon , as shown in equation 23. once the output current exceeds the overcurrent trip level, v imon will exceed v ocp and a comparator will trigger the converter to begin overcurrent protection procedures. at the beginning of an overcurr ent shutdown, the controllers turn off both upper and lower mosfets and lowers vr_rdy. the controllers will then attempt to soft-start after a delay of typically 8xtd1. if the overcurrent fault remains, the trip-retry cycles will continue un til either the controller is disabled or the fault is cl eared. note that the energy delivered during trip-retry cycl ing is much less than during full-load operation, so there is no thermal hazard. i ocp 100 10 6 ? r set n3 ?? ?? dcr 400 ? --------------------------------------------------------------- = (eq. 22) i ocp 3v ocp r set n ??? dcr r iout 400 ?? ---------------------------------------------------- - = (eq. 23) isl6333, isl6333a, isl6333b, isl6333c 31 fn6520.3 october 8, 2010 individual channel overcurrent limiting the controllers have the ability to limit the current in each individual channel without shutting down the entire regulator. this is accomplished by cont inuously comparing the sensed currents of each channel with a constant 140a ocl reference current, as shown in figure 18. if a channel?s individual sensed current exceeds this ocl limit, the ugate signal of that channel is immediately forced low, and the lgate signal is forced high. this turns off the upper mosfet(s), turns on the lowe r mosfet(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. that channel?s ugate signal will not be able to return high until the sensed channel current falls back below the 140a reference. during vid-on-the-fly transit ions the ocl trip level is boosted to prevent false overcu rrent limiting events that can occur. starting from the beginning of a dynamic vid transition, the overcurrent trip level is boosted to 196a. the ocl level will stay at this boosted level until 50s after the end of the dynamic vid transition, at which point it will return to the typical 140a trip level. mosfets general design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a multi-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include sc hematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis, which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole co mponents are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical soluti ons are those in which each phase handles between 25a and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but thes e designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 24, i m is the maximum continuous output current, i p-p is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is depe ndent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mo sfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low(1) and p low(2) . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. 0a 0v output current, 50a/div figure 19. overcurrent behavior in hiccup mode output voltage, 500mv/div (eq. 24) p low 1 () r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lp-p () 2 1d ? () ? 12 --------------------------------------- - + ? = (eq. 25) p low 2 () v don () f s i m n ------ i p-p 2 ----------- + ?? ?? ?? t d1 ? i m n ------ i p-p 2 ----------- ? ?? ?? ?? ?? t d2 ? + ?? = isl6333, isl6333a, isl6333b, isl6333c 32 fn6520.3 october 8, 2010 when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 26, the required time for this commutation is t 1 and the approximated associated power loss is p up(1) . at turn-on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 27, the approximate power loss is p up(2) . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up(3) shown in equation 28. finally, the resistive part of the upper mosfet is given in equation 29 as p up(4). . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 26, 27, 28 and 29. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipat ed in the integrated drivers located in the controllers. since there are a total of three drivers in the controller pack age, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipatio n in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of +125c. the maximum allowable ic power dissipation for the 7x7 qfn package is approximately 3.5w at room temperature. see ?layout considerations? on page 37 for thermal transfer improvement suggestions. when designing the controllers in to an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets a nd the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 30 and 31, respectively. in equations 30 and 31, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q *vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. (eq. 26) p up 1 () v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? p up 2 () v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? (eq. 27) p up 3 () v in q rr f s ?? = (eq. 28) p up 4 () r ds on () d i m n ----- - ?? ?? ?? 2 i p-p 2 12 ---------- + ?? (eq. 29) figure 20. typical upper-gate drive turn-on path figure 21. typical lower-gate drive turn-on path p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 30) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 31) q 1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q 2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate isl6333, isl6333a, isl6333b, isl6333c 33 fn6520.3 october 8, 2010 the total gate drive power loss es are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the pow er dissipated in the upper drive path resistance, p dr_up , the lower drive path resistance, p dr_up , and in the boot strap diode, p boot . the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 20 and 21 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as calculated in equation 32: inductor dcr curren t sensing component selection the controllers sense each individual channel?s inductor current by detecting the voltage across the output inductor dcr of that channel (as described in the ?continuous current sensing? on page 21). as figure 22 illustrates, an r-c network is required to accurately sense the inductor dcr voltage and convert this information into a curr ent, which is propor tional to the total output current. the time constant of this r-c network must match the time constant of the inductor l/dcr. follow the steps below to choose the component values for this rc network. 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, and the value for c 1 chosen in step 1, into equation 33 to calculate the value for r 1 . once the r-c network components have been chosen, the effective internal r isen resistance must then be set. the r isen resistance sets the gain of the load line regulation loop as well as the gain of the channel-current balance loop and the overcurrent trip level. the effective internal r isen resistance is set through a single resistor on the r set pin, r set . use equation 34 to calculate the value of r set . in equation 34, dcr is the dcr of th e output inductor at room temperature, i ocp is the desired overcurrent trip level, and n is the number of phases. it is recommended that the desired overcurrent trip level, i ocp , be chosen so that it?s 30% larger then the maximum load current expected. due to errors in the inductance or dcr it may be necessary to adjust the value of r 1 to match the time constants correctly. the effects of time c onstant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in figure 23. follow the steps below to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). for example, with l = 1h and dcr = 1m , set the oscilloscope to 500s/div. 2. record v1 and v2 as shown in figure 23. 3. select new values, r 1(new) , for the time constant resistor based on the original value, r 1(old) , using equation 35. 4. replace r 1 with the new value and check to see that the error is corrected. repeat the procedure if necessary. p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 32) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = r 1 l dcr c 1 ? ------------------------- = (eq. 33) figure 22. dcr sensing configuration i n - + isen- sense isl6333 internal ugate r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen v c (s) + - isen+ lgate mosfet driver rset r set vcc circuit r set dcr 100 10 6 ? ---------------------------- i ocp n ------------- - 400 3 --------- - ?? = (eq. 34) r 1new () r 1old () v 1 v 2 ---------- ? = (eq. 35) isl6333, isl6333a, isl6333b, isl6333c 34 fn6520.3 october 8, 2010 . loadline regulation resistor if load line regulation is desired on the isl6333 and isl6333a, the idroop pin should be connected to the fb pin in order for the internal average sense current to flow out across the loadline regulation resistor, labeled r fb in figure 7. the isl6333b and isl6333c always have the load line regulation enabled. the r fb resistor value sets the desired loadline required for the application. the desired loadline, r ll , can be calculated by equation 36 where v droop is the desired droop voltage at the full load current i fl . based on the desired loadline, the loadline regulation resistor, r fb , can be calculated from equation 37. in equation 37, r ll is the loadline resistance; n is the number of active channels; dcr is the dcr of the individual output inductors; and r set is the rset pin resistor. if no loadline regulation is required on the isl6333 and isl6333a, the idroop pin should be left unc onnected. to choose the value for r fb in this situation, please refer to ?compensation without load-line regulation? on page 35. imon pin resistor a copy of the average sense cu rrent flows out of the imon pin, and a resistor, r imon , placed from this pin to ground can be used to set the overcurrent protection trip level. based on the desired overcurrent trip threshold, i ocp , the imon pin resistor, r imon , can be calculated from equation 38. apa pin component selection a 100a current flows into the apa pin and across r apa to set the apa trip level. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. use equation 39 to set r apa to get the desired apa trip level. an apa trip level of 500mv is recommended for most applications. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation as described in load-line regulation, there are two distinct methods for achieving these goals. compensation with load-line regulation the load-line regulated converter behaves in a similar manner to a peak current m ode controller because the two poles at the output filt er l-c resonant frequency split with the introduction of current informat ion into the control loop. the final location of th ese poles is determ ined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . see figure 24. since the system poles and zero are affected by the values of the components that are me ant to compensate them, the solution to the system equation becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. figure 23. time constant mismatch behavior v 1 v out i tran v 2 i r ll v droop i fl ------------------------ - = (eq. 36) r fb r ll nr set ?? dcr --------------------------------------- 3 400 --------- - ? = (eq. 37) (eq. 38) r imon r set n ? dcr i ocp ? ------------------------------- - 3.381 400 -------------- - ? = r apa v apa trip () 100 10 6 ? -------------------------------- - 500mv 100 10 6 ? ---------------------------- - 5k === (eq. 39) figure 24. compensation configuration for load-line regulated isl6333 circuit isl6333 comp c c r c r fb fb vdiff c 2 (optional) idroop isl6333, isl6333a, isl6333b, isl6333c 35 fn6520.3 october 8, 2010 in equation 40, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude, as described in the ?electrical specifications? on page 13. once selected, the compensation values in equation 40 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 40 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 24). keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 25, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient per formance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a good general rule is to choose f hf =10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equation 41, r fb is selected arbitrarily. the remaining compensation components are then selected. in equation 41, l is the per-channel filter inductance divided by the number of active channel s; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude, as described in the ?electrical specifications? on page 13. output filter design the output inductors and the ou tput capacitor bank together to form a low-pass filter responsible for smoothing the 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v p-p lc ? ?? ? ? v in ---------------------------------------------------------- ? = c c v in 2 v p-p r fb f 0 ?? ? ? ----------------------------------------------------- - = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v pp 2 ? () ? 2 f 0 2 lc ??? v in ---------------------------------------------------------------- - ? = c c v in 2 ? () 2 f 0 2 v p-p r fb lc ? ?? ? ? -------------------------------------------------------------------------------------- - = case 2: (eq. 40) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v p-p l ?? ? ? v in esr ? --------------------------------------------- - ? = c c v in esr c ?? 2 v p-p r fb f 0 l ?? ? ? ? ----------------------------------------------------------------- - = case 3: figure 25. compensation circuit without load-line regulation isl6333 comp c c r c r fb fb vsen c 2 c 1 r 1 c c v in 2 f hf lc ? 1 ? ?? ? () ? 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = r c v pp 2 ?? ?? ? 2 f 0 f hf lcr fb ?? ??? v in 2 f hf lc ? 1 ? ?? ? () ? ---------------------------------------------------------------------------------------- - = r 1 r fb cesr ? lc ? c esr ? ? ------------------------------------------- - ? = c 1 lc ? c esr ? ? r fb ------------------------------------------- - = c 2 v in 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = (eq. 41) isl6333, isl6333a, isl6333b, isl6333c 36 fn6520.3 october 8, 2010 pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of i nductor current and regulator response, the output voltage in itially deviates by an amount as shown in equation 42. the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 17 and equation 2), a voltage develops across the bulk capacitor esr equal to i c(p-p) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p- p(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 44 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 45 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be se lected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in the ?mosfets general design guide? on page 31 and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t . figure 26 and equation 46 are provided to assist in se lecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input curr ent flowing into the upper mosfets. their rms current ca pacity must be sufficient vesl di dt ---- - ? esr i ? + (eq. 42) l esr v in nv ? out ? ?? ?? v out ? f s v in v p-p max () ?? ------------------------------------------------------------------- - ? (eq. 43) l 2ncv o ??? i () 2 --------------------------------- v max i esr ? () ? ? (eq. 44) l 1.25 nc ?? i () 2 ---------------------------- - v max i esr ? () ? v in v o ? ?? ?? ?? (eq. 45) r t 10 10.61 1.035 f s () log ? () ? [] = (eq. 46) figure 26. r t vs switching frequency 10 100 500 50k 100k 1m 2m switching frequency (hz) r t (k ) isl6333, isl6333a, isl6333b, isl6333c 37 fn6520.3 october 8, 2010 enough to handle the ac compone nt of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a three-phase design, use figure 27 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l,(p-p) ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculat ed. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. figures 28 and 29 provide the same input rms current information for two-phase and single-phase designs respectively. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using the isl6333 family of controllers. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. figure 27. normalized input-capacitor rms current for 3-phase converter duty cycle (v in/ v o ) 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 28. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 29. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in /v o ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6333, isl6333a, isl6333b, isl6333c 38 fn6520.3 october 8, 2010 via connection to ground plane island on power plane layer island on circuit plane layer key figure 30. printed circuit board power planes and islands heavy trace on circuit plane layer c boot1 r 1 c 1 c 3 r ofs r fb c bin1 (c hfout ) c bout (cf1) (cf3) r t c ref locate close to ic locate near load; (minimize connection locate near switching transistors; (minimize connection path) (minimize connection path) vid4 vid5 vr_rdy vid3 vid2 vid1 vcc isl6333 vid0 fs ofs ref load psi# en gnd vid6 vid7 ss +5v isen2- isen2+ isen1- isen1+ +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc2_3 r ss c boot2 c bin2 c 1 r 1 c 1 r 1 path) imon r imon apa comp fb dvc vsen rgnd +5v vcc rset c 2 r 2 r dvc c dvc r apa r set (cf4) isen3- isen3+ +12v phase3 ugate3 boot3 lgate3 puvcc c boot3 c bin3 c 1 r 1 (cf2) pvcc1 (cf1) byp1 vdiff idroop r ugate r ugate r ugate isl6333, isl6333a, isl6333b, isl6333c 39 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6520.3 october 8, 2010 the power components should be placed first, which includes the mosfets, input and output ca pacitors, and the inductors. it is important to have a symmetric al layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidistant plac ement of the controller to the power trains it controls throug h the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capabili ty of all sets of mosfets. when placing the mosfets, try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input bulk capacitors should be placed close to the drain of the upper fe ts and the source of the lower fets. locate the output inductors and output capacitors between the mosfets and the load. the high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next or on the capacitor solder pad. the critical small components include the bypass capacitors for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense components. locate the vcc/pvcc bypass capacitors as close to the controller as possible. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. figure 30 shows the connections of the critical components for the converter. note that capacitors c xx(in) and c xx(out) could each represent numerous physical capacitors. dedicate one solid layer, usually the one u nderneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase termina l to output inductors short. the power plane should support the input power and output power nodes. use copper filled po lygons on the top and bottom circuit layers for the phase nod es. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to reduce their overall impedance and inductance. they s hould be sized to carry at least one ampere of current (0.02? to 0.05?). going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibilit y of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. current sense component placement and trace routing one of the most critical aspec ts of the controller regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sense components must be placed as close to their respective isen+ and isen- pins on the controller as possible. the sense traces that connect the r-c sense components to each side of the output induc tors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or pla nes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performanc e in high current, high switching frequency applicatio ns, connecting the thermal gnd pad of the controllers to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controllers be placed in a direct path of airflow if possible to help thermally manage the part. isl6333, isl6333a, isl6333b, isl6333c 40 fn6520.3 october 8, 2010 isl6333, isl6333a, isl6333b, isl6333c package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 5, 4/10 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05 |
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